VERIFICATION ENGINEER/ASIC RTL / SOC DESIGN ENGINEER
Company: TetraMem - Accelerate The World
Location: Fremont
Posted on: September 24, 2024
|
|
Job Description:
TetraMem is a fast-growing venture-backed well-funded startup
company working on the next generation computing platforms with
unique ReRAM-based in-memory computing technologies. We are hiring
in multiple positions from software to hardware.
In this team you be part of a world-leading IC design team
responsible for the development and deployment of hardware
solutions for a revolutionary computing system, which we believe
can bring up the energy efficiency by another two orders of
magnitude, and completely changes the AI IoT industry. It is based
on our unique computing memory device, which has SoTA bit-level per
cell, nonvolatile, excellent retention, and endurance. We offer a
very competitive compensation and benefits package (including
medical, unlimited PTO, and 401k) that commensurate with
experience.
Pay Range:$110,000 - $250,000
ASIC RTL/SoC Design EngineerRequirements:--- MS with 5+ years of
experience or PhD in Electrical Engineering with emphasis on
RTL/SoC/digital design--- Experience with Verilog and system
Verilog--- Experience with VCS, and UVM design verification
tools.--- Experience with pre-layout simulation and post-layout
simulation--- Understanding of the design flow. Ability to work
with the backend team--- Familiarity with AMBA APB AXI Protocol---
Familiarity with RISC/Arm or other core architectures--- Ability to
create innovative architecture and solutions to customer
requirements--- Ability to work in startup environment and work
both independently and as a team player, with the ability to
provide technical leadership to other members of the engineering
team.
Experience in one or more of the following areas considered a
strong plus:--- FPGA/ASIC design of image processing systems---
Working knowledge of SoC architecture such as CPU, GPU or
accelerators--- Familiarity with: UVM, place-and-route, STA,
EM/IR/Power
ASIC/SoC Design Verification Engineer In this role, you will be
part of a world-class IC design team responsible for defining and
developing a revolutionary computing system, which we believe can
reduce the energy consumption of AI processing by more than two
orders of magnitude over conventional digital solutions. This will
completely disrupt the AI IoT landscape. It is based on our unique
computing memory technologies with multi-bit-level capacity per
cell, which is nonvolatile with excellent retention and
endurance.We offer a very competitive compensation, commensurate
with experience, and a full benefits package including medical,
professional PTO, 401k, and other perks.
Responsibilities: - Collaborate with design engineers and
architects to define, document and implement detailed test plans
for the SoC design verification. - Build and maintain
infrastructure/environment for automation verification of SoC
architecture, function and performance. - Develop reusable
testbench, constrained-random/directed testcases, and verification
associated behavioral module for both of block levels and system
levels. - Develop regression strategy, methodology and
tools(scripts). Define and measure the function coverage. Close
verification holes for design releases and tape-out. - Work with
design engineers to debug and identify root causes of simulation
failure. - Support test engineers for post-silicon validation. -
Mentor and coach team members and junior engineers. Drive
verification efficiency.
Qualifications: - MS with 8+ years of relevant experience or PhD
(with 3+ years of experience) in Electrical Engineering, Computer
Engineering, Computer Science or related degree. - In depth
knowledge of UVM/OVM, Semiformal Verification, assertion-based
verification as well as hardware and software co-verification
methodology. - Extensive experience of building verification
infrastructure, test planning, coverage closure, testbench and
testcases development for function/performance verification. -
Proficient experience with Verilog, System Verilog,
Python/Perl/TCL/Shell scripting, C/C++, System C and industry
mainstream ISAs assembly coding. - Familiarity with MIPI, AMBA
(APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core. - Experience in
verifying designs at both of RTL level and post-P&R gate level.
- Ability to work in a startup environment, and to work both
independently and as a team player with the ability to provide
technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a
strong plus: - Working knowledge of AI/ML Computing, GPU, ISP
architectures and accelerators - Experience in verifying mix-signal
design and interface of digital and analog. - Experience of design
verification for highspeed IO such as PCIE and DDR.
Keywords: TetraMem - Accelerate The World, Fremont , VERIFICATION ENGINEER/ASIC RTL / SOC DESIGN ENGINEER, Engineering , Fremont, California
Click
here to apply!
|